Co-Packaged Copper

Overview

Co-Packaged Copper (CPC) is an interconnect substrate technology developed by TE Connectivity that integrates a dense copper signal layer directly into the chip package, bridging the chip I/O and the rack backplane with 1,024 or more differential pairs on a 110×110mm substrate. The NanoLGA+ connector format achieves sub-0.4mm differential pitch — enabling this density in a footprint comparable to a high-bandwidth memory die. CPC targets data lane speeds from 224G (current standard) to 448G (next generation), using PAM4 modulation with a trajectory toward PAM6/PAM8 to extend copper's viability.

CPC addresses the interconnect wall by replacing traditional PCB trace routing — which degrades signal integrity at high speeds — with a tightly coupled, high-density substrate assembly. The co-packaging concept is analogous to co-packaged optics but implemented in copper, avoiding the power consumption and laser failure-mode penalties of optical solutions at shorter reach distances (chip to backplane, chip to chip within a rack). TE positions CPC as one of the densest copper interconnect implementations available commercially as of 2025.