Empowering Scale-Up and Scale-Out Networking With Samtec CPX Architecture: CPC & CPO

Author: Samtec (Speaker name not provided) Collection: 2025 OCP Global Summit - Expo Hall Sessions

Summary

Samtec presents its CPX (Co-Package Interconnect) architecture as a unified form factor that supports both co-packaged copper (CPC) and co-packaged optics (CPO) through the same socket on the same chip package. The CPX socket delivers 6.4 Tbps bidirectional bandwidth (32TX + 32RX at 200 Gbps per lane) in a beachfront width of only 14.7mm x 16.7mm, soldered to the package substrate by the OSAT using standard 0.5mm pitch SMT technology. This approach eliminates the need to choose between CPC and CPO at chip design time.

The key differentiator versus alternative CPO approaches is that CPX is electrically detachable, meaning optical engines can be built and tested independently by any optical vendor (like OSFP transceivers today) and simply plugged into the CPX socket at the ODM, achieving near-100% yield at assembly. Alternative CPO requires soldering all photonic ICs onto the chip package with 512-lane yield testing at the OSAT, resulting in much lower yields and higher complexity. A comparison table shows CPX supports both CPO and CPC (alternative CPO supports only CPO), is electrically detachable (alternative is not), achieves 102T density in a 95mm x 95mm package, has ~100% yield, low complexity, and maintains the same ecosystem as front-panel pluggable.

For scale-up, CPX enables passive copper backplane connections at 200 Gbps over 2m reach, saving 4.5 dB insertion loss versus going off-package. This enables 512+ lanes in 1 RU with the lowest cost architecture. For scale-out, the same CPX socket accepts co-packaged optics or flyover cables to OSFP. The CPX form factor scales to 448G PAM4, potentially enabling 400T switches in 1U. Molex has signed on as a second source, and multiple optical vendors are preparing CPX socket feasibility demonstrations for OFC in early 2026.