SerDes

Overview

SerDes (Serializer/Deserializer) is the high-speed electrical signaling technology used to transmit data between chips, between chiplets within a package, and across PCB traces and cables at the rack level. In AI data center contexts, SerDes speed determines the port bandwidth density of network switches and the off-chip memory/IO bandwidth available to accelerators.

The industry has progressed from 56G NRZ to 112G PAM4 to 224G PAM4, with 448G under active development. However, the physical constraints of copper (skin effect, dielectric loss, impedance at high frequency) create a practical speed ceiling. As of October 2025, some engineers place the copper physical limit around 400G per lane, beyond which the signal integrity challenges become insurmountable without transitioning to optical interconnects — the primary motivation for Co-Packaged Optics adoption.