Towards Wafer-scale Optical Interconnect Relying on Silicon Photonics and Advanced 3D Assembly

Author: Peter Ossieur, Portfolio Director, imec, Belgium Collection: 2026 OCP EMEA Summit - Photonics

Summary

This presentation by imec's Peter Ossieur makes the case that copper-based scale-up interconnect is approaching a fundamental wall, and that optical interconnect — combined with silicon photonics and advanced 3D assembly — is the only credible path to scaling AI accelerator fabrics beyond single-rack boundaries. The talk is organized around a precise problem statement: by H2 2026 the scale-up shoreline density is 0.6 Tb/s/mm at ~1 kW GPU power; by 2032 the required density jumps to 10 Tb/s/mm with GPU power at 3 kW. Co-packaged optics (CPO) in the conventional "fast-and-narrow" configuration using DSP-driven high-speed links at 4–5 pJ/bit would consume 1.25 kW for the optics alone on a 250 Tb/s interface — physically untenable.

Ossieur presents two imec technology roadmaps as the solution. The first, OIO2.5D, keeps the optical engine on a silicon interposer adjacent to the XPU, eliminates DSP by adopting NRZ modulation at lower baud rates, and recovers bandwidth density through DWDM (32 or 64 wavelengths) on compact silicon disk modulators with 2.1 µm radius and FSR >6.4 THz. Combined with Cu hybrid-bonded low-capacitance Ge photodetectors and 22 nm FDSOI EIC technology, OIO2.5D is projected to close a link at ~2 pJ/bit and 2 Tb/s/mm — still resulting in ~500 W for the optics. The second, more ambitious roadmap, OIO3D, places active PICs directly on a passive silicon-nitride Optical Interconnect Wafer (OIW) using hybrid bonding and evanescent coupling, and integrates an optical circuit switch on-wafer. OIO3D targets 0.5 pJ/bit and 8 Tb/s/mm, reducing optics power to ~500 W for a 250 Tb/s interface.

The talk also details the specific photonic device work enabling both roadmaps: a C-band Franz-Keldysh electroabsorption modulator (FK-EAM) on GeSi with >100 GHz electro-optical bandwidth demonstrated at 400G/lane on a 300 mm wafer; Ge PIN photodetectors with >100 GHz bandwidth and <3 fF capacitance; a disk modulator with 26–31 GHz modulation bandwidth and TP ~8 dB from 1 Vpp drive; a 32-channel DWDM filter in 300 mm SiPho technology with ~2 dB channel insertion loss and ~370 GHz/mW thermal tuning efficiency; and emerging work on III-V (InP/GaAs) and barium titanate (BTO) modulators grown on 300 mm silicon via collaboration with Veeco using hydride MBE. A wafer-scale OIO3D vision integrates up to 16 GPUs, HBM, laser arrays, and network processors on a single OIW with total optics dissipation of ~50 kW — underscoring the thermal management challenge as the final barrier.