Accelerated AI With P4 DPUs: Next-Level Flexibility, Performance & Scale on AMD AI NICs

Author: Shane Corbin, Product Management, AMD NTSG Collection: 2025 OCP Global Summit - Expo Hall Sessions

Summary

AMD presents its Pensando Pollara 400 AI NIC as a unified scale-out networking platform delivering 10% better RoCEv2 performance than competitors and 25% better performance with UEC-RDMA versus RoCEv2, while enabling up to 50% lower fabric cost through multi-plane networking that eliminates the core switch tier. The Pollara 400 is P4-programmable, shipping to 20+ customers across cloud, hyperscaler, and neo-cloud segments, with a new OCP 3.0 form factor announced at the summit. Key UEC innovations include adaptive packet spray across 256 paths, in-order delivery using memory address headers, path-aware congestion control with selective retransmission, and probe-based packet loss detection.

The roadmap reveals the AMD Helios AI rack arriving mid-2026, combining EPYC Venice CPUs, Instinct MI400 GPUs, and next-generation Vulcano 800G AI NICs built on 3nm process. Helios features a 72-GPU scale-up domain across 18 compute trays (4 MI400 GPUs per tray) interconnected via six UALink-over-Ethernet scale-up switches, with 3x the scale-out bandwidth per GPU (3x 800G) compared to the current Pollara/MI300 configuration. For a 128K GPU cluster, multi-plane architecture using four independent Tomahawk 5-based planes showed 50% lower cost versus a three-tier fat-tree with Jericho3/Ramon3 big-buffer switches.