CXL (Compute Express Link)

Overview

CXL (Compute Express Link) is an open industry standard interconnect built on the PCIe physical layer, enabling cache-coherent memory expansion, pooling, and sharing between CPUs and accelerators. CXL is cited alongside OCP, PCI-SIG, the UALink Consortium, and JEDEC as one of the key standards communities the AI ecosystem should engage with for open AI infrastructure. Astera Labs' Leo smart memory controllers implement CXL, enabling expanded memory capacity for AI workloads that require large context windows.