Cisco Silicon One P200
Overview
The Cisco Silicon One P200 is a 51.2 Tbps full-duplex routing ASIC announced at OCP Global Summit 2025. It delivers an industry-leading 20 billion packets per second with routing-level capabilities while achieving switch-level power efficiency. Key architectural innovations:
- Fully shared deep packet buffer: Unlike conventional routers that partition buffer memory per port, the P200 uses a single shared buffer pool that can dynamically assign capacity to any port under congestion, reducing waste and enabling much denser buffering without per-port overprovisioning.
- Run-to-completion engine: The pipeline dynamically adapts to workload traffic patterns in real time, described by Cisco as "always optimal" for mixed workloads.
- Built-in root-of-trust: Security is integrated at the silicon level, guaranteeing device integrity from manufacture to end-of-life, with data-plane authenticity protecting against sideband attacks.
Two-tier leaf-spine with 512 leaves and 256 P200 spines reaches 13 petabits of aggregate bandwidth; a three-tier topology extends to 3.355 exabits. The P200 physically resembles the G200 switch silicon (deep buffers + encryption) more than traditional routing ASICs, achieving router flexibility at switch power efficiency levels.
The P200 powers the Cisco 8223-64EF (OSFP800, 3RU) and 8223-64E (QSFP-DD800, 3RU) routers — both sampling at OCP 2025 — and the Alibaba QuantumCat (128×400G QSFP112, 4RU, ALiNOS).
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