Harnessing Time Coordinated Computing (TCC) to Enable the Next Generation of Applications from the Cloud to the Edge

Author: David Zage, Intel (Contributors: Zoltan Fodor, Chris Hall, Keith Wiles) Collection: 2025 OCP Global Summit - Expo Hall Sessions

Summary

Intel's Time Coordinated Computing (TCC) is a comprehensive set of platform features ensuring low-latency, real-time compute performance by solving jitter and latency issues on commodity hardware. The presentation covers how TCC technologies -- including PCIe Precision Time Measurement (PTM), Timed General-Purpose IO (TGPIO), cache allocation technology, and IRQ optimizations -- are integrated into Intel Xeon 6 processors and Intel Ethernet E830/E835 network adapters (up to 200 Gbps throughput) to enable deterministic workloads from data center to edge.

A key innovation demonstrated is time source consolidation on Xeon 6, where multiple independent oscillators (25 MHz crystals and 156.25 MHz crystals) are replaced with a unified Digital Phase-Locked Loop (DPLL) clock source. Testing across four scenarios showed that moving from independent oscillators to a single DPLL source achieves TGPIO-to-TGPIO jitter of 0.53 ns and TGPIO-to-E830 network time synchronization of 20.72 ns -- reaching the theoretical limit of the 40 ns TGPIO firing cycle (plus/minus 20 ns). The system uses PHC2SYS with PTM to synchronize Intel E825 and E830 PHC clocks with system time, and PTP4L/PHC for time discipline.

Three transformation drivers require TCC: the shift to AI-driven real-time automation, the shift to software-defined workloads requiring portable timing guarantees, and the shift to secure converged networks combining IT and OT traffic while maintaining SLA guarantees.