P4 Programmable Networking

Overview

P4 (Programming Protocol-independent Packet Processors) is a domain-specific language for defining data plane behavior in network devices (NICs and switches) without hardware changes. Originally designed to enable customer-defined SDN stacks — encapsulation, firewall, load balancing, micro-segmentation, security protocols like IPSec and PSP — AMD Pensando extended it with P4DMA, which adds descriptor-to-packet programmability enabling custom NVMe/RDMA/TCP storage protocols and, most recently, custom AI networking transports.

AMD's P4 RDMA implementation on Pollara 400 supports standard RoCEv2, UEC-enhanced RoCEv2, or fully custom RDMA transports via the P4 SDK. The critical advantage for AI at scale is live in-service protocol updates: when a transport protocol validated at 1,000–2,000 GPU scale encounters new failure modes at million-GPU scale, the P4 architecture allows updating the deployed NIC firmware across the entire cluster without traffic disruption — something impossible with fixed-function hardware.

AMD Pensando has been developing P4-based NICs for 7–8 years, accumulating P4 software components that carry forward across NIC generations (Pollara 400 → Vulcano).