COMPUTEX 2026 CEO Keynote: Marvell — Connectivity is the Next Defining Challenge of AI

Author: Matt Murphy, CEO, Marvell Technology; with Jensen Huang (NVIDIA CEO) and Dr. Tian Wu (ASE CEO) Collection: Computex 2026

Summary

Marvell CEO Matt Murphy delivered the opening Day 1 keynote at Computex 2026, presenting a comprehensive case that connectivity — not compute or memory — is now the defining bottleneck and growth opportunity in AI infrastructure. Murphy traced Marvell's decade-long transformation from a $2.3B consumer-oriented semiconductor company (with less than 10% of revenue from data center in 2016) into a $11.4B (consensus FY26E) pure-play data infrastructure semiconductor company, with over 75% of revenue from data center and ~40% annual growth. The transformation involved ~$22.5B in strategic acquisitions (Cavium, Avera, Aquantia, Inphi, Innovium, Celestial AI, Xconn), ~$18B in organic investment, and ~$4.5B in divestitures (Wi-Fi, G.hn, LTE, Multimedia, Automotive Ethernet), for a total committed capital of ~$36B. Consensus estimates put FY27 revenue at $16.4B.

Murphy's central technical thesis is that as AI workloads require tens of thousands to millions of accelerators working together, the architecture of the interconnect between them — not the raw compute or memory — determines system performance. He introduced the concept of the "copper wall": the physical distance limit beyond which copper cables can no longer carry high-bandwidth signals, which is moving inside the rack as bandwidth scales from 200 Gbps per lane (2.5m copper reach) to 400 Gbps and beyond. This wall movement creates a 10x explosion in optical connection count and will drive the next major wave of semiconductor demand. Marvell is positioning itself as the only company with a complete end-to-end optical connectivity portfolio from millimeters (die-to-die serdes) to kilometers (coherent DSP for inter-data-center links), and is shipping co-packaged optics (CPO) silicon demonstrators today.

Two key announcements headlined the event: the Marvell Ara Family 1.6T PAM4 digital signal processor (DSP) — the industry's first 3nm 1.6T PAM4 DSP — and the Marvell Teralynx T100, a 100-terabit Ethernet switch, also on 3nm and purpose-built for AI data centers with the industry's lowest latency. Jensen Huang appeared on stage to validate the Marvell-NVIDIA strategic partnership (anchored by NVIDIA's $2B investment in Marvell), describing NVLink Fusion as the mechanism for integrating NVIDIA's platform with customer ASICs and Marvell's photonic interconnect technology. ASE CEO Dr. Tian Wu also joined to discuss the decade-long manufacturing partnership enabling the optical supply chain scale-up.