Expanding Horizons: Data Center Market Outlook And MediaTek's Leading AI ASIC Technologies

Author: Hing Jao, MediaTek Collection: 2025 OCP Global Summit - Expo Hall Sessions

Summary

MediaTek presents its data center ASIC capabilities, highlighting the growing complexity of AI accelerator silicon and interconnects. Training compute demand is growing approximately 10x per year (based on the last six years), while physical design advancement grows only about 2x, creating a gap addressed by chiplet architecture, die-to-die interconnects, and scale-up/scale-out networking. The company has invested in data center and enterprise solutions since 2011, launching Ethernet switch products in 2016 and building what it describes as the world's largest info packaging and hyper CoWoS designs.

Current AI accelerators use 3-4x reticle sizes, but the next generation is moving to 7-8x and then 12-13x reticle sizes, requiring transitions from 2.5D to 3.5D packaging (necessary above 8-9x reticle). Key technology areas include compute (2nm to A16 process nodes), interconnects (224G to 448G SerDes, electrical to optical), advanced packaging (CoWoS, EMIB, SoIC, Foveros), memory (HBM to custom HBM with customer-defined base die logic, digital CIM), integrated power delivery (IVR for high current density), and thermal management (logic-on-memory stacking for heat dissipation).

MediaTek describes three interconnect categories: die-to-die (UCI, proprietary MediaTek Link/MINK), chip-to-chip (SerDes, PCIe, retimers), and port-to-port (electrical/optical with DSP, transimpedance amplifiers, silicon photonics). The transition from MPC to CPC to CPO depends on throughput and lane count: MPC works up to ~10 Tbps with 200G SerDes, CPC at higher throughput with 200-300G SerDes, and CPO becomes the only option above ~60 Tbps with 400G SerDes. MediaTek is developing its own EIC/PIC for CPO with detachable socket connectors, demonstrated at this year's OCP at up to 400 Gbps per fiber.