HBM High Bandwidth Memory

Overview

HBM (High Bandwidth Memory) is a stacked DRAM architecture in which multiple DRAM die layers are vertically stacked with through-silicon vias (TSVs) and connected to a logic die or GPU/NPU die via a 2.5D interposer. Each HBM stack presents an extremely wide memory interface (1024 bits per stack), delivering order-of-magnitude higher bandwidth than conventional GDDR while occupying a smaller footprint adjacent to the compute die on the interposer.

HBM3E is the fourth-generation specification (after HBM, HBM2, HBM2E, HBM3), and the 12H variant (12 DRAM die layers) provides the highest capacity per stack. Rebellions' REBEL-Q integrates four HBM3E (12H) stacks on an ICube-S 2.5D interposer, providing 4.8 TB/s aggregate HBM bandwidth and 144 GB total HBM capacity — key to supporting 2 PFLOPS FP8 compute without memory bottlenecks during large language model inference. Samsung Foundry offers HBM as part of its advanced memory portfolio, alongside the ICube-S packaging required to integrate it.