Taeksang Song, Corporate VP of DRAM Solution Engineering at Samsung Semiconductor, presented Samsung's full next-generation memory portfolio at OCP Global Summit 2025 on October 14, 2025 in San Jose. The presentation covered the entire AI memory hierarchy — from HBM4/HBM4E and custom HBM for GPU-attached high-bandwidth applications, through DDR5 RDIMM/MRDIMM and low-power LPDDR-based modules (LPCAMM2, SOCAMM2), to Processing-in-Memory and CXL memory expansion with compute capability. Samsung argued that as AI evolves from generative to agentic to physical AI, memory becomes the foundational enabler requiring specialized, power-efficient solutions at every tier.

Key Takeaways

• HBM4 doubles I/O lanes to 2048 (vs. 1024 for HBM3/HBM3E) and uses a FinFET-process base die, breaking the energy-efficiency plateau seen with HBM3/HBM3E; HBM4E will extend these gains further.
• Samsung's advanced logic process for HBM4 creates ~25% additional base die area, enabling custom HBM with customer-specific logic (memory controllers, AI engines) and near-memory compute architectures.
• Samsung 12nm-class 32Gb DDR5 is the industry's first 32Gb mono-die, delivering 15% lower power vs. prior gen and enabling up to 256 GB RDIMM modules for generative AI servers.
• MRDIMM reaches 12.8 Gbps pin speed (1.6x vs. 8.0 Gbps RDIMM) and 512 GB capacity via an MDB multiplexor data buffer managing two pseudo-channels simultaneously.
• LPDDR6 hits 10.7 Gbps/pin and 114.1 GB/s aggregate bandwidth — highest in mobile DRAM — with 20% better power efficiency vs. LPDDR5X, targeting both AI servers and edge/mobile devices.
• LPCAMM2 delivers 136 GB/s at 8.5 Gbps/pin with 60% better power efficiency and 64% smaller form factor than DDR5 SoDIMM; SOCAMM2 brings the same bandwidth to AI servers with 44% less power than DDR5 RDIMM.
• LPDDR5X-PIM demonstrated 4.47x performance and 3.44x energy efficiency improvement over standard NPU-LP5 for on-device LLM inference by executing arithmetic operations in parallel across all DRAM banks.
• Samsung CMM-D 2.0 CXL module (128–256 GB, 36 GB/s) is in mass production; CMM-D 3.0 with CXL 3.x and PCIe Gen 6 targets 1 TB and 72 GB/s; the industry-first CXL 3.1 product is planned for Q4 2025.
• AI workloads' relative insensitivity to memory latency makes fabric-attached CXL memory a viable complement to near-compute solutions for scaling AI infrastructure capacity.