Switch ASIC Scaling

Overview

Switch ASIC scaling refers to the progression of switching ASIC aggregate bandwidth capacity over time, driven by AI workload demands for ever-higher GPU cluster interconnect bandwidth. The consensus roadmap as of 2025:

The Broadcom Tomahawk 6 (sampling June 2025, production early 2026) is the representative 102.4T ASIC, with 2,355B transistors; it enables 64-port 1.6TbE density using 224 Gbps SerDes.

Beyond raw capacity, ASIC scaling introduces significant engineering challenges:

• SerDes evolution: Scaling to 128-port 800G configurations requires migrating from 100G to 200G SerDes per lane, tightening signal integrity constraints on switch PCB design.
• Thermal management: 128-port 800G switches exceed the thermal limits of air cooling; optical transceiver loads at 1.6T speeds can exceed 24W per port, making DLC-cooled 2RU switches a mainstream requirement by 2026.
• Cabling complexity: Each doubling of port bandwidth increases the fiber plant complexity, especially when transitioning from pluggable to CPO or expanded beam optics.