Advanced Packaging

Overview

Advanced Packaging refers to multi-die integration technologies that go beyond traditional monolithic chip design to co-locate compute, memory (HBM), IO, and increasingly optical (CPO) components within a single package. The primary technologies include 2.5D interposer-based packaging (CoWoS, CoWoS-L with Intel EMIB), 3D stacking (through-silicon vias, hybrid bonding), and 3.5D packaging (combining stacked and side-by-side die arrangements).

TSMC's CoWoS has been the dominant 2.5D technology, growing reticle size from 1x in 2016 to approximately 9x by 2023. The speaker at OCP 2025 assessed that 9–10x represents the practical physical boundary for 2.5D packaging, driving the transition to 3.5D as the next generation. 3.5D packaging provides greater die area and improved performance-to-TCO ratios required by cloud service providers as AI model complexity continues to scale.

Modern AI accelerator packages must now integrate not just compute and HBM, but also IO chiplets (224G/448G SerDes), copper-to-optical bridges, and co-packaged optical engines — making Advanced Packaging a co-equal pillar of AI silicon strategy alongside process node and microarchitecture.