Chiplet Architecture

Overview

Chiplet Architecture is a design methodology that replaces a single large monolithic System-on-Chip (SoC) with multiple smaller, specialized dies (chiplets) that are co-packaged using high-speed die-to-die interconnects. Each chiplet is optimized independently — compute dies on the most advanced process node for energy efficiency, IO dies on a mature node for cost, HBM for memory bandwidth, and optical engines for CPO — then assembled into a single package using 2.5D, 3.5D, or 3D advanced packaging technologies.

MediaTek shipped its first chiplet design in mass production approximately 2020 (one large compute die + eight IO chiplets with 100G SerDes), predating the widespread industry adoption of chiplet terminology. In 2018, MediaTek demonstrated Hybrid CoWoS — assembling two 1.5x reticle packages (each with one compute die and four HBM stacks) onto a sub-package, achieving an effective 3x reticle size before TSMC offered it natively.

Standard interconnects for chiplet integration include UCIe (Universal Chiplet Interconnect Express) for multi-vendor interoperability, and proprietary high-bandwidth die-to-die interfaces for maximum bandwidth density within a vendor ecosystem.