Driving-Innovation-in-Data-Center-Computing-And-ASIC-Technologies-Presented-by-MediaTek

At OCP Global Summit 2025, MediaTek Senior Marketing Director C.K. Peng presented the company's strategy for driving innovation in data center computing and ASIC technologies. The talk covered the explosive growth of the custom AI accelerator market (projected to exceed $40B by 2028 at a >46% CAGR), the gap between Moore's Law and AI compute demand, and MediaTek's four-pillar ASIC platform spanning advanced process nodes, IP portfolio, ecosystem partnerships, and flexible engagement models. Key technology investments include 2nm/A16 process readiness, 224G-to-448G SerDes, 3.5D packaging as the successor to 2.5D CoWoS, Custom HBM, and Co-Packaged Optics expected to reach mass production one to two years ahead of the original 2030 target.

Key Takeaways

The custom AI accelerator TAM grew from $6.1B in 2023 to a projected >$40B in 2028 (CAGR >46%), with some analysts forecasting $80–100B by 2030.
Moore's Law delivers only ~2x/year improvement in compute, interconnect, and memory bandwidth, while AI training compute demand has grown ~10x/year over the last six years, creating a structural gap that only advanced packaging and custom silicon can close.
MediaTek is near-ready for 2nm production and actively moving to TSMC A16, with 224G SerDes in production and 448G in development; 400G may represent the physical copper speed limit, making optical transition necessary.
CoWoS reticle size has evolved from 1x to 9x over a decade; 9–10x is approaching the 2.5D physical limit, making 3.5D packaging the next mandatory step for higher compute density and better performance/TCO for CSPs.
Co-Packaged Optics (CPO) mass production, originally targeted for ~2030, is expected to arrive one to two years earlier following NVIDIA's GTC 2025 CPO announcement, signaling faster-than-expected ecosystem readiness.
MediaTek's first chiplet design was in mass production circa 2020 (one compute die + eight 100G IO chiplets), and its 2018 Hybrid CoWoS design achieved an effective 3x reticle by stacking two 1.5x packages before TSMC offered 3x natively.
MediaTek is developing Custom HBM (non-standard base dies) with hyperscalers and memory vendors to exceed JEDEC HBM5 bandwidth limits, alongside Compute-in-Memory solutions to reduce memory latency.