Experiences in Designing a Better NVMe Controller

Tim Amundsen (ScaleFlux) and Matt Bromage (ARM) present their collaborative development of next-generation NVMe SoCs at OCP Global Summit 2025. The talk traces escalating OCP Storage specification demands—220 pages and 475+ requirements by 2025, up from 56 pages—and explains ScaleFlux's strategic decision to adopt the ARM Cortex-R82 core for both Gen 5 (FC5116) and Gen 6 (FC6116) products. ARM provides detailed benchmarks showing R82 achieves 44% power reduction at equivalent performance versus Cortex-R8, while ScaleFlux reports 30% core utilization reduction and Gen 6 performance delivery under a 6.5W power budget without a lithography node change.

Key Takeaways

• The OCP Storage NVMe specification grew from 56 pages and ~175 requirements to 220 pages and 475+ requirements by 2025, reflecting accelerating demands for security, manageability, latency monitoring, FDP, and telemetry.
• ScaleFlux launched SFX 3000 (PCIe Gen 4) in 2022 with ARM A53, then moved to Cortex-R82 starting with the FC5116 (PCIe Gen 5), enabling a straightforward firmware port to FC6116 (PCIe Gen 6) on the same architecture.
• ARM Cortex-R82 delivers 81% per-core performance improvement over R5 and 36% over R8 (CoreMark/MHz), with 64-bit addressing up to 1 TB versus the prior 4 GB limit.
• At 1.15 GHz with Vnom minus 150 mV, Cortex-R82 achieves equivalent R8 performance with 44% less power; at 1.15 GHz nominal voltage the reduction is 18%.
• ScaleFlux's FC6116 Gen 6 SoC targets market-leading NVMe performance under a 6.5W power budget and aims to be the first third-party Gen 6 NVMe SoC to market, avoiding a lithography node change through R82 architectural efficiency.
• Core utilization for garbage collection and data path management dropped 30%, and tightly coupled memory enabled OCP latency monitoring compliance and FDP-enable bit activation without a process node change.