TE Connectivity presented at OCP Global Summit 2025 its interconnect, power, and thermal solutions for next-generation high-density AI data centers. Pranav Garg (VP Strategy/BD/Marketing) and Ganesh Srinivasan (VP Product Management) outlined five key market trends — rising GPU density, doubling interconnect speeds (224G to 448G), rack power scaling toward 1MW, increasing thermal loads, and geo-resilient supply chain demands — and detailed TE's product responses across signal (co-packaged copper, over-the-board, backplanes) and power (48V/HVDC bus bars, liquid-cooled bus bars, liquid-cooled I/O) domains. TE highlighted being first-to-market with liquid-cooled bus bars, now deployed at Meta, capable of 5x higher current density than air-cooled equivalents, and co-demonstrated an active backplane with Astera Labs.

Key Takeaways

• The "interconnect wall" — not the memory wall — is the primary physical bottleneck in AI architectures; interconnect cannot scale as fast as compute by physics.
• GPU density in AI racks is progressing from 36 to 72 to 144 to 288 GPUs per rack (Kyber architecture), requiring architectural innovations and denser interconnect products.
• Interconnect data lane speeds are doubling every ~1.5 years: 56G → 112G → 224G → 448G, compressing AI rack generation cycles from ~3 years to ~1.5 years.
• Rack power is scaling from ~100kW today toward 1MW; air-cooled bus bars top out at ~200kW, making liquid-cooled bus bar technology critical above that threshold.
• TE Connectivity's liquid-cooled bus bar (first-to-market) delivers 5x current capacity in the same form factor vs. air-cooled, with ORv3/ORv3-HPR compatibility and configurations from 200kW to 750kW (1.2MW in development); Meta is an early production deployer.
• TE's co-packaged copper (CPC) solution routes 1,024+ differential pairs on a 110×110mm substrate from chip to backplane, supporting 224G to 448G — one of the densest implementations in the industry.
• HVDC (±400V) connectors cut transmission losses 10–20% and save up to 50% rack space vs. 48V; voltage architectures are transitioning from 48V toward 400V and 800V.
• Copper will coexist with optics in AI racks due to power efficiency, cost, and scaling advantages; PAM4 is the current standard, PAM6/PAM8 are being evaluated to extend copper to 336G/448G.
• TE is partnering with Astera Labs (active backplane), Meta (liquid-cooled bus bar), and Marvell/Broadcom/Seagate to integrate active chips into interconnect solutions.
• Each 1.6T optical transceiver consumes ~40W; liquid-cooled I/O is critical to managing thermal loads from high-density optical ports in large AI clusters.