Co-Designing for AI: Open Standards and Ecosystems Driving the Future of Infrastructure

At OCP Global Summit 2025 in San Jose, Rebellions hardware lead Wonguk Kim and Samsung Foundry's Thomas Mermans jointly presented the co-design strategy behind their AI chiplet ecosystem. Rebellions detailed its accelerator roadmap from the 2022 ION single-die chip through the 2024 REBEL-Q (a four-die HBM3E chiplet with 2 PFLOPS FP8 on Samsung 4nm) and the 2025 REBEL-IO tape-out. Mermans then updated the audience on the four-party AI CPU chiplet platform — announced at OCP 2024 — combining Arm Neoverse V3 CSS, Samsung Foundry 2nm, ADTechnology implementation, and Rebellions NPU chiplets, with the new OCP 2025 milestone being a fully-placed V3 core floorplan targeting 3.5–4.0 GHz.

Key Takeaways

Rebellions' REBEL-Q, taped out in 2024 on Samsung 4nm, integrates four REBEL_H NPU dies and four HBM3E stacks in a single ICube-S package delivering 2 PFLOPS FP8, 4.8 TB/s HBM bandwidth, 144 GB memory, 512 MB on-chip SRAM, and 4 TB/s UCIe-A die-to-die bandwidth at 600 W TDP.
The four-party AI CPU chiplet platform (Arm + Samsung Foundry + ADTechnology + Rebellions) announced at OCP 2024 targets LLM inference, combining a 64-core Arm Neoverse V3 CSS CPU chiplet with REBEL_H NPU chiplets on Samsung 2nm; the platform claims ~3x power and performance efficiency over existing solutions.
New at OCP 2025: ADTechnology completed a fully-placed Neoverse V3 core floorplan on Samsung Foundry 2nm targeting 3.5–4.0 GHz clock frequency, confirming the implementation is on track.
Samsung Foundry positions itself as the only foundry offering a one-stop shop covering advanced process (2nm GAA, its third GAA iteration), Samsung HBM memory with custom base die, advanced packaging (2.5D/2.3D/3D), and the SAFE ecosystem of 100+ IP, EDA, cloud, DSP, MDI, and OSAT partners.
Samsung Foundry has ongoing US manufacturing investment at its Austin fab (long in mass production) and the new Taylor fab in Texas, in addition to South Korean campuses at Giheung, Hwaseong, and Pyeongtaek.
The chiplet architecture allows reconfiguring package compositions without new mask costs, enabling customers to combine REBEL-Q, REBEL-IO, REBEL-MEM, and REBEL-CPU chiplets to match diverse compute, memory, and scalability requirements.